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WF512K64-XG4WX5
HI-RELIABILITY PRODUCT
512Kx64 5V FLASH MODULE
FEATURES
Access Times of 70, 90, 120, 150ns Packaging
PRELIMINARY*
5 Volt Programming. 5V 10% Supply. Low Power CMOS, 6.5mA Standby Embedded Erase and Program Algorithms TTL Compatible Inputs and CMOS Outputs Built-in Decoupling Caps for Low Noise Operation Page Program Operation and Internal Program Control Time Weight WF512K64-XG4WX5 - 20 grams typical
* This data sheet describes a product under development, not fully characterized, and is subject to change without notice. Note: Programming information available upon request.
116 lead, 40mm square, Hermetic CQFP (Package 504) 100,000 Erase/Program Cycles Minimum Sector Architecture 8 equal size sectors of 64KBytes each Any combination of sectors can be concurrently erased. Also supports full chip erase Organized as 512Kx64, user configurable as 1Mx32, 2Mx16, or 4Mx8. Commercial, Industrial and Military Temperature Ranges
FIG. 1
PIN CONFIGURATION FOR WF512K64-XG4WX5 TOP VIEW
I/O2 I/O1 I/O0 VCC WE2 CS2 NC A0 A1 A2 A3 A4 WE1 CS1 NC CS8 WE8 A5 A6 A7 A8 A9 NC CS7 WE7 VCC I/O63 I/O62 I/O61
A0-18 OE 1 512K x 8 WE1 CS 1
BLOCK DIAGRAM
WE2 CS2 WEx CSx WE8 CS8
2 512K x 8
......
8
8 512K x 8
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 116 115 114 113 112 111 110 109 108 107 106 105 104 103
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74
I/O60 I/O59 I/O58 I/O57 I/O56 GND I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 GND I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND I/O39 I/O38 I/O37 I/O36 I/O35
8
8
8
I/O0-7
I/O8-15
I/O...
I/O56-63
PIN
I/O0-63 A0-18 WE1-8 CS1-8 OE VCC GND NC
DESCRIPTION
Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected
May 1999 Rev.2
I/O29 I/O30 I/O31 VCC WE3 CS3 NC NC A18 A17 A16 A15 WE4 CS4 OE CS5 WE5 A14 A13 A12 A11 A10 NC CS6 WE6 VCC I/O32 I/O33 I/O34
1
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
WF512K64-XG4WX5
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Supply Voltage Range (VCC) Signal voltage range (any pin except A9) (2) Storage Temperature Range Lead Temperature (soldering, 10 seconds) Data Retention (Mil Temp) Endurance (write/erase cycles) (Mil Temp) A9 Voltage for sector protect (VID) (3) -55 to +125 -2.0 to +7.0 -2.0 to +7.0 -65 to +150 +300 20 years 100,000 cycles min. -2.0 to +14.0 V Unit C V V C C Parameter OE capacitance WE capacitance CS capacitance Data I/O capacitance Address input capacitance
CAPACITANCE (TA = +25C)
Symbol COE CWE CCS CI/O CAD Conditions VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VI/O = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz Max 100 20 20 20 100 Unit pF pF pF pF pF
This parameter is guaranteed by design but not tested.
NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns. 3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) A9 Voltage for Sector Protect Symbol VCC VIH VIL TA TA VID Min 4.5 2.0 -0.5 -55 -40 11.5 Max 5.5 VCC + 0.5 +0.8 +125 +85 12.5 Unit V V V C C V
DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Input Leakage Current Output Leakage Current VCC Active Current for Read (1) VCC Active Current for Program or Erase (2) VCC Standby Current VCC Static Current Output Low Voltage Output High Voltage Symbol ILI ILOx32 ICC1 ICC2 ICC4 ICC3 VOL VOH1 Conditions VCC = 5.5, VIN = GND to VCC VCC = 5.5, VIN = GND to VCC CS = VIL, OE = VIH, f = 5MHz CS = VIL, OE = VIH VCC = 5.5, CS = VIH, f = 5MHz VCC = 5.5, CS = VIH IOL = 8.0 mA, VCC = 4.5 IOH = -2.5 mA, VCC = 4.5 0.85
X
Min
Max 10 10 380 480 13 1.2 0.45
Unit A A mA mA mA mA V V
VCC
Low VCC Lock-Out Voltage VLKO 3.2 4.2 V NOTES: 1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/ MHz, with OE at VIH. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
2
WF512K64-XG4WX5
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (VCC = 5.0V, VSS = 0V, TA = -55C to +125C)
Parameter Write Cycle Time Write Enable Setup Time Chip Select Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Chip Select Pulse Width High Duration of Byte Programming Operation (1) Chip and Sector Erase Time (2) Read Recovery Time Chip Programming Time Chip Erase Time (3) NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH1 is 1sec. 3. Typical value for Chip Erase Time is 8sec. Symbol Min tAVAV tWLEL tELEH tAVEL tDVEH tEHDX tELAX tEHEL tWHWH1 tWHWH2 tGHEL 0 11 64 tWC tWS tCP tAS tDS tDH tAH tCPH 70 0 45 0 45 0 45 20 300 15 0 11 64 -70 Max Min 90 0 45 0 45 0 45 20 300 15 0 11 64 -90 Max Min 120 0 50 0 50 0 50 20 300 15 0 11 64 -120 Max 150 0 50 0 50 0 50 20 300 15 ns ns ns ns ns ns ns ns s sec ns sec sec -150 Unit
FIG. 2
AC TEST CONDITIONS
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL = 0, VIH = 3.0 5 1.5 1.5 Unit V ns V V
AC TEST CIRCUIT
NOTES: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 y. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
3
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
WF512K64-XG4WX5
AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED (VCC = 5.0V, TA = -55C to +125C)
Parameter Write Cycle Time Chip Select Setup Time Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High Duration of Byte Programming Operation (1) Sector Erase Time (2) Read Recovery Time before Write VCC Set-up Time Chip Programming Time Output Enable Setup Time Output Enable Hold Time (4) Chip Erase Time (3) NOTES: 1. Typical value for tWHWH1 is 7s. 2. Typical value for tWHWH1 is 1sec. 3. Typical value for Chip Erase Time is 8sec. 4. For Toggle and Data Polling. tOES tOEH 0 10 64 Symbol Min tAVAV tELWL tWLWH tAVWH tDVWH tWHDX tWHAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS 0 50 11 0 10 64 tWC tCS tWP tAS tDS tDH tAH tWPH 70 0 45 0 45 0 45 20 300 15 0 50 11 0 10 64 -70 Max Min 90 0 45 0 45 0 45 20 300 15 0 50 11 0 10 64 -90 Max Min 120 0 50 0 50 0 50 20 300 15 0 50 11 -120 Max Min 150 0 50 0 50 0 50 20 300 15 -150 Max ns ns ns ns ns ns ns ns s sec ns s sec ns ns sec Unit
AC CHARACTERISTICS READ ONLY OPERATIONS (VCC = 5.0V, TA = -55C to +125C)
Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output High Z (1) Output Enable High to Output High Z (1) Output Hold from Address, CS or OE Change, whichever is First 1. Guaranteed by design, but not tested Symbol Min tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX tRC tACC tCE tOE tDF tDF tOH 0 70 70 70 35 20 20 0 -70 Max Min 90 90 90 35 20 20 0 -90 Max Min 120 120 120 50 30 30 0 -120 Max Min 150 150 150 55 35 35 -150 Max ns ns ns ns ns ns ns Unit
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
4
WF512K64-XG4WX5
FIG. 3
AC WAVEFORMS FOR READ OPERATIONS
tDF
tOH
Addresses Stable
tRC
tOE
tACC
tCE
WE
OE
Addresses
5
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
Outputs
CS
High Z
Output Valid
High Z
WF512K64-XG4WX5
FIG. 4
WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED
tRC
tOH
tDF
tOE
PA
Data Polling
tAH
tWHWH1
PA
tAS
tWPH
tDH
5555H
tGHWL
tWC
tWP
tCS
A0H
PD
D7
DOUT
Addresses
WE
OE
CS
tDS
NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence.
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
6
5.0 V
Data
tCE
WF512K64-XG4WX5
FIG. 5
AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
SA
2AAAH
5555H
2AAAH
5555H
tWPH
5555H
tWP
AAH tDS
tAS
tGHWL
tCS
tDH
55H
tAH
80H
AAH
55H
10H/30H
Addresses
WE
OE
CS
Data
NOTE: 1. SA is the sector address for Sector Erase.
7
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
VCC
tVCS
WF512K64-XG4WX5
FIG. 6
AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS
tDF
tOH
High Z
D7 = Valid Data
D0-D7 Valid Data tWHWH 1 or 2 Data D0-D6 D0-D6 = Invalid tOE
tOE
tCH
tOEH
tCE
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
8
WE
OE
CS
D7
D7
WF512K64-XG4WX5
FIG. 7
ALTERNATE CS CONTROLLED PROGRAMMING OPERATION TIMINGS
PA
Data Polling
tAH
tWHWH1
PA
tAS
tGHEL
tCP
tCPH
tDH A0H
5555H
tWC
tWS
PD WE OE CS tDS
Addresses
D7
DOUT
Notes: 1. PA represents the address of the memory location to be programmed. 2. PD represents the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates the last two bus cycles of a four bus cycle sequence.
9
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
5.0 V
Data
WF512K64-XG4WX5
PACKAGE 504:
116 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4W)
5.1 (0.200) MAX
39.6 (1.56) 0.38 (0.015) SQ
1.27 (0.050) 0.1 (0.005)
PIN 1 IDENTIFIER Pin 1
12.7 (0.500) 0.5 (0.020) 4 PLACES 5.1 (0.200) 0.25 (0.010) 4 PLACES
1.27 (0.050) REF 38 (1.50) REF 4 PLACES
0.38 (0.015) 0.08 (0.003) 68 PLACES
0.25 (0.010) 0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W F 512K64 - XXX G4W X 5
VPP PROGRAMMING VOLTAGE 5 = 5V DEVICE GRADE: M = Military Screened I = Industrial C = Commercial
-55C to +125C -40C to +85C 0C to + 70C
PACKAGE TYPE: G4W = 116 Lead 40mm Ceramic Quad Flat Pack, CQFP (Package 504) ACCESS TIME (ns) ORGANIZATION, 512K x 64 User configurable as 1M x 32, 2M x 16 or 4M x 8 Flash WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520
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